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CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
Integrated Device Technology, Inc.
IDT72413
FEATURES:
* First-ln/First-Out Dual-Port memory--45MHz * 64 x 5 organization * Low-power consumption -- Active: 200mW (typical) * RAM-based internal structure allows for fast fall-through time * Asynchronous and simultaneous read and write * Expandable by bit width * Cascadable by word depth * Half-Full and Almost-Full/Empty status flags * IDT72413 is pin and functionally compatible with the MMI67413 * High-speed data communications applications * Bidirectional and rate buffer applications * High-performance CMOS technology * Available in plastic DIP, CERDIP and SOIC * Military product compliant to MIL-STD-883, Class B * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis. It is expandable in bit width. All speed versions are cascadable in depth. The FIFO has a Half-Full Flag, which signals when it has 32 or more words in memory. The Almost-Full/Empty Flag is active when there are 56 or more words in memory or when there are 8 or less words in memory. The IDT72413 is pin and functionally compatible to the MMI67413. It operates at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering applications. The IDT72413 can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers. The IDT72413 is fabricated using IDTs high-performance CMOS process. This process maintains the speed and high output drive capability of TTL circuits in low-power CMOS. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
OUPUT ENABLE (OE)
DATAIN (D0-4 ) (MR) MASTER RESET INPUT READY SHIFT IN (IR)
FIFO INPUT STAGE
64 x 5 MEMORY ARRAY
FIFO OUTPUT STAGE
DATA OUT (Q0-4 )
(SO) INPUT CONTROL LOGIC REGISTER CONTROL LOGIC OUTPUT CONTROL LOGIC (OR)
SHIFT OUT OUPUT READY
(SI)
FLAG CONTROL LOGIC
HALF-FULL (HF) ALMOST-FULL/ EMPTY (AF/E)
2748 drw 01
The IDT logo is a registered trademark of Integrated Device Technology,Inc. FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2748/7
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE HF IR SI D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9 10 20 19 18
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vcc AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR
2748 drw 02
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current
Commercial -0.5 to +7.0
Military -0.5 to +7.0
Unit V
VTERM
P20-1, C20-1, & SO20-2
17 16 15 14 13 12 11
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
-55 to +125 -65 to +135 -65 to +150 50
C C C mA
DIP/SOIC TOP VIEW
NOTE: 2748 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF
2748 tbl 02
NOTE: 1. This parameter is sampled and not 100% tested. 2. Characterized values, not currently listed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VCC GND VIH VIL
(1)
Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Input Low Voltage
Min. 4.5 4.5 0 2.0 --
Typ. 5.0 5.0 0 -- --
Max. Unit 5.5 5.5 0 -- 0.8 V V V V V
2748 tbl 03
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5.0V 10%, TA = -55C to +125C)
Symbol IIL IIH VOL Parameter Low-Level Input Current High-Level Input Current Low-Level Output Current Test Conditions VCC = Max., GND VI VCC VCC = Max., GND VI VCC VCC = Min. IOL (Q0-4) Mil. IOL (IR, OR)(1) IOL (HF, AF/E) VOH High-Level Output Current VCC = Min. IOH (Q0-4) IOH (IR, OR) IOH (HF, AF/E) IOS IHZ ILZ ICC(3) Supply Current
(2)
Min. -10 -- 12mA 8mA 8mA -4mA -4mA -4mA -20 -- -20 -- -- 2.4 --
Max. -- 10 0.4
Unit A A V
Com'l. 24mA
--
V
Output Short-Circuit Current Off-State Output Current
VCC = Max. VO = 0V VCC = Max. VO = 2.4V VCC = Max. VO = 0.4V VCC = Max., OE=HIGH Mil. Inputs LOW, f=25MHz Com'l.
-110 20 -- 70 60
mA A mA
NOTES: 2748 tbl 04 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25mHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. For frequencies greater than 25MHz, ICC = 60mA + (1.5mA x [f - 25MHz]) commercial and ICC = 70mA + (1.5mA x [f - 25MHz]) military.
OPERATING CONDITIONS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5.0V 10%, TA = -55C to +125C)
Commercial Military & Commercial Military & Commercial
Symbol tSIH tIDS tIDH tSOH(1) tSOL tMRW tMRS
(1)
Parameters Shift in HIGH Time Shift in LOW TIme Input Data Set-up Input Data Hold Time Shift Out HIGH Time Shift Out LOW Time Master Reset Pulse Master Reset Pulse to SI
Figure 2 2 2 2 5 5 8 8
IDT72413L45 Min. Max. 9 11 0 13 9 11 20 20 -- -- -- -- -- -- -- --
IDT72413L35 Min. Max. 9 17 0 15 9 17 30 35 -- -- -- -- -- -- -- --
IDT72413L25 Min. Max. 16 20 0 25 16 20 35 35 -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns
tSIL(1)
NOTE: 2748 tbl 05 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1F directly between VCC and GND with very short lead length is recommended.
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5.0V 10%, TA = -55C to +125C)
Commercial Symbol fIN tIRL(1) tIRH
(1)
Mil. & Com'l IDT72413L35 Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- 35 18 20 35 18 20 -- 20 28 28 28 28 25 28 28 -- -- 5 28 28 28 28 28 28 12 12 15 15
Mil. & Com'l IDT72413L25 Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- 25 28 25 25 28 25 -- 20 40 30 30 30 35 40 40 -- -- 7 40 40 40 40 40 40 15 15 20 20 ns Unit MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameters Shift In Rate Shift In to Input Ready LOW Shift In to Input Ready HIGH Shift Out Rate Shift Out to Output Ready LOW Shift Out to Output Ready HIGH Output Data Hold Previous Word Output Data Shift Next Word Data Throughput or "Fall-Through" Master Reset to Output Ready LOW Master Reset to Input Ready LOW Master Reset to Outputs LOW Master Reset to Half-Full Flag Master Reset to AF/E Flag Input Ready Pulse HIGH Ouput Ready Pulse HIGH Output Ready HIGH to Valid Data Shift Out to AF/E HIGH Shift In to AF/E Shift Out to AF/E LOW Shift In to AF/E HIGH Shift In to HF HIGH Shif Out to HF LOW
Figure 2 2 2 5 5 5 5 5 4, 7 8 8 8 8 8 8 4 7 5 9 9 10 10 11 11 12 12
IDT72413L45 Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- 45 18 18 45 18 19 -- 19 25 25 25 25 20 25 25 -- -- 5 28 28 28 28 28 28 12 12 15 15
fOUT tORL(1) tORH tODS tPT tMRORL
(2) (1)
tODH(1)
tMRIRH(3) Master Reset to Input Ready HIGH tMRIRL tMRQ tMRHF tMRAFE tIPH
(3)
tOPH(3) t ORD tAEH tAEL tAFL tAFH tHFH tHFL tPHZ tPLZ tPLZ
(3) (3) (3) (3) (3)
Output Disable Delay
Output Enable Delay
12 12
tPHZ
NOTES: 2748 tbl 06 1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1F directly between VCC and GND with very short lead length is recommended. 2. If the FIFO is full, (IR = HIGH), MR forces IR to go LOW, and MR causes IR to go HIGH. 3. Guaranteed by design but not currently tested.
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
2748 tbl 07
STANDARD TEST LOAD 5V R1 OUTPUT R2 TEST POINT 30pF*
DESIGN TEST LOAD 5V 2K
30pF*
or equivalent circuit
*Including scope and jig
2748 drw 03
RESISTOR VALUES FOR STANDARD TEST LOAD
IOL 24mA 12mA 8mA R1 200 390 600
Figure 1. Output Load
R2 300 760 1200
2748 tbl 08
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO has an available memory location; Output Ready (OR) signals when there is valid data on the output. Output Enable (OE) provides the capability of three-stating the FIFO outputs.
DATA OUTPUT
Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, Output Ready will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FlFOs output when it is empty. When the FIFO is not empty Output Ready (OR) goes LOW on the LOW-to-HlGH transition of Shift Out.
FALL-THROUGH MODE
The FIFO operates in a Fall-Through Mode when data gets shifted into an empty FIFO. After the fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH. A Fall-Through Mode also occurs when the FIFO is completely full. When data is shifted out of the full FIFO a location is available for new data. After a fall-through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data can be written to the FIFO. The fall-through delay of a RAMbased FIFO (one clock cycle) is far less than the delay of a Shift register-based FIFO.
FIFO RESET
The FIFO must be reset upon power up using the Master Reset (MR) signal. This causes the FIFO to enter an empty state signified by Output Ready (OR) being LOW and Input Ready (IR) being HIGH. In this state, the data outputs (Q0-4) will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads input data into the first word location of the FIFO and causes the lnput Ready to go LOW. On the HlGHto-LOW transition of Shift In, the write pointer is moved to the next word position and Input Ready (lR) goes HlGH indicating the readiness to accept new data. If the FIFO is full, Input Ready will remain LOW until a word of data is shifted out.
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS: INPUTS:
DATA INPUT (D0-4) Data input lines. The IDT72413 has a 5-bit data input.
INPUT READY(IR) When Input Ready is HIGH, the FIFO is ready for new input data to be written to it. When IR is LOW, the FIFO is unavailable for new input data, Input Ready is also used to cascade many FIFOs together, as shown in Figure 13 in the Applications section. OUTPUT READY (OR) When Output Ready is HIGH, the output (Q0-4) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. Output Ready is also used to cascade many FIFOs together, as shown in Figure 13 in the Applications section. OUTPUT ENABLE (OE) Output Enable is used to enable the FIFO outputs onto a bus. Output Enable is active LOW. ALMOST-FULL/EMPTY FLAG (AFE) Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words) or 1/8 from empty (8 or less words).
CONTROLS:
SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-4 lines. The data has to meet set-up and hold time requirements with respect to the rising edge of SI. SHIFT OUT (SO) Shift Out controls the outputs data from the FIFO. MASTER RESET (MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a Master Reset. Master Reset is active LOW. HALF-FULL FLAG (HF) Half-Full Flag signals when the FIFO has 32 or more words in it.
OUTPUTS:
DATA OUTPUT (Q0-4) Data output lines, three-state. The IDT72413 has a 5-bit output.
1/fIN
TIMING DIAGRAMS
1/fIN SHIFT IN tSIH t SIL tIRH INPUT READY tIDH INPUT DATA tIDS
Figure 2. Input Timing
2748 drw 04
tIRL
SHIFT IN
(7)
(2) (1)
(4)
(5)
INPUT READY
(3)
(6)
INPUT DATA
STABLE DATA
2748 drw 05
Figure 3. The Machanism of Shifting Data Into the FIFO NOTES: 1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied. 2. Input Data is loaded into the FIFO. 3. Input Ready goes LOW indicating the FIFO is unavailable for new data. 4. The write pointer is incremented. 5. The FIFO is ready for the next word. 6. If the FIFO is full, then the Input Ready remains LOW. 7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4). 5.02 6
IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
(2)
SHIFT OUT
(3)
SHIFT IN
(4)
(5)
INPUT READY
(1)
t PT
tIPH
INPUT DATA
NOTES: 1. FIFO is initially full. 2. Shift Out pulse is applied. 3. Shift In is held HIGH. 4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH).
STABLE DATA
2748 drw 06
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
1/fOUT SHIFT OUT tSOH t SOL
(2)
1/fOUT
tRH OUTPUT READY tORD tODS tODH OUTPUT DATA
(1)
tORL
A-DATA
B-DATA
C-DATA
2748 drw 07
NOTES: 1. This data is loaded consecutively A, B, C. 2. Output data changes on the falling edge of SO after a valid Shift Out sequence, i.e., OR and SO are both high together. Figure 5. Output TIming
SHIFT OUT
(7)
(2) (1)
(4)
(5)
OUTPUT READY
(3)
(6)
OUTPUT DATA
A-DATA A or B
B-DATA
2748 drw 08
NOTES: 1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied. 2. Shift Out goes HIGH causing the next step. 3. Output Ready goes LOW. 4. Read pointer is incremented. 5. Output Ready goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns. 6. If the FIFO has only one word loaded (A DATA) , Output Ready stays LOW and the A-DATA remains unchanged at the outputs. 7. Shift Out pulses applied when Output Ready is LOW will be ignored. Figure 6. The Mechanism of Shifting Data Out of the FIFO
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT t PT OUTPUT READY
(1)
tOPH
2748 drw 09
NOTE: 1. FIFO initailly empty. Figure 7. tPT and tOPH Specification
MASTER RESET
(1)
t MRW
INPUT READY t MRIRL
(1)
t MRIRH
OUTPUT READY tMRORL SHIFT IN t MRS
DATA OUTPUTS tMRQ HALF-FULL FLAG t MRHF ALMOST FULL/ EMPTY FLAG t MRAFE
NOTE: 1. FIFO is partially full.. Figure 8. Master Reset Timing
2748 drw 10
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT OUT tSOH ALMOST FULL/EMPTY
(1)
t AEH SHIFT IN
t SIH
tAEL
NOTE: 1. FIFO contains 9 words (one more than Almost-Empty). Figure 9. tAEH and tAEL Specifications
2748 drw 11
SHIFT IN tSIH ALMOST FULL/EMPTY
(1)
t AFH SHIFT OUT
t SOH
tAFL
NOTE: 1. FIFO contains 55 words (one short of Almost-Full). Figure 10. tAFH and tAFL Specifications
2748 drw 12
SHIFT IN tSIH HALF-FULL
(1)
t HFH SHIFT OUT
NOTE: 1. FIFO contains 31 words (one short of Half-Full).
tSOH
tHFL
2748 drw 13
Figure 11. tHFL and tHFH Specifications
3V OE tPZL WAVEFORM 1
(1)
VT
VT 0V 4.5V VT tPLZ 0.5V 1.5V VOL VOH 1.5V 0V 0.5V
t PZH WAVEFORM 2
(2)
tPHZ VT
2748 drw 14 NOTES: 1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. 2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
Figure 12. Enable and Disable
5.02
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS
OUTPUT ENABLE HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR SHIFT OUT
COMPOSITE INPUT READY
HF IR SI D0 D1 D2 D3 D4
OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR
COMPOSITE OUTPUT READY
SHIFT IN
HF IR SI D0 D1 D2 D3 D4
OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR MASTER RESET
2748 drw 15
NOTE: 1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement is due to the different fall-through times of the FIFOs. Figure 13. 64 x 15 FIFO with IDT72413
8-BITS SYSTEM 1 TWO IDT72413 64 x 8 SI SO OR IR
8-BITS SYSTEM 2
ENBL SI INTERRUPT
IO RDY INTERRUPT
ALMOST-FULL/ EMPTY HALF-FULL FLAG
2748 drw 16
NOTE: 1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13. Figure 14. Application for IDT72413 for Two Asynchronous Systems
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IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SHIFT IN INPUT READY
DATA IN
SI IR D0 D1 D2 D3 D4
MR
OR SO Q0 Q1 Q2 Q3 Q4
SI IR D0 D1 D2 D3 D4
MR
OR SO Q0 Q1 Q2 Q3 Q4
OUTPUT READY SHIFT OUT
DATA OUT
NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 15. 128 x 5 Depth Expansion
MR
2748 drw 17
ORDERING INFORMATION
IDT XXXXX X X X X Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0C to+70C) B Military (-55C to+125C)Compliant to MIL-STD-883, Class B P D SO 45 35 25 L Plastic DIP (300 mils wide) Cerdip (300 mils wide) Small Outline IC Com'l. Only Com'l. and Mil Com'l. and Mil Low Power
2748 drw 18
Shift Frequency (fs)Speed in MHz
72413 64 x 5 FIFO
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